From: mmm@cup.portal.com (Mark Robert Thorson)

>From time to time, computer architects must face the patent system.
This requires working with a patent attorney to develop a
description of a product under development in the highly formalized
language and style of patent.  In addition to being a major pain in the
neck and time waster, it usually hits early in the development cycle,
when the designer is deeply involved in finalizing the design and
debugging the prototypes.

This can be a frustrating process, because it has to be done right the
first time.  Adding material is usually impossible, because it means
accepting a new filing date.  If in the meantime a public disclosure of
the invention has been made, all foreign patent rights are lost.

Although new material cannot be added, it is a little-known fact that
any amount of material can be supplied with the patent application
at the time of filing, then deleted from the application.  It is this
material which can be added back (undeleted).  It can be added back
whole or in part.

To this end, the following paragraph was developed.  It is
recommended that this paragraph (or a variant of it customized to
your invention) is interleaved with every other paragraph in your
patent application:

"The dynamic pipelined parallel cache SCSI DMA graphics
communications CISC RISC processor port disk memory controller is
equipped with can handle transfer control receive transmit buffer
calculate operate produce up to a minimum maximum of 1 2 4 8 16
32 K M G baud bits bytes words pixels 8- 16- 32- 64- 80- bit
integers IEEE-compatible floating-point numbers per second cycle
memory bank page sector disk row line column frame
communications channel.  This is useful useless required provides for
fast slow high low performance resolution speed density cost power
consumption interactive memory math calculation graphics I/O
communications bandwidth cycles."

By selectively undeleting individual words, we can form an infinite
variety of new sentences, such as:

"The SCSI port can transfer up to 4 M bytes per second.  This is
useful for high performance I/O bandwidth."

"The cache controller handles a maximum of 128 K memory.  This
provides fast memory cycles."

"The pipelined RISC processor can operate on 80-bit IEEE-compatible
floating-point numbers.  This is required for high-resolution math."

"The graphics controller can produce up to 16 pixels per cycle.  This
provides fast interactive graphics."

A somewhat longer version of this paragraph forms the basis for my
patent application "A Digital Machine for Operating on Data".  :-)